5.7.6.11 CSI2DC SSP Interrupt Status Register
| Name: | CSI2DC_SSPISR |
| Offset: | 0x28 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RE[3:0] | |||||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LE[3:0] | LS[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FE[3:0] | FS[3:0] | ||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 19:16 – RE[3:0] Reserved Short Packet Interrupt Status
| Value | Description |
|---|---|
| 0 | A bit cleared at position i in the field RE indicates that no Reserved Short Packet interrupt is pending for virtual channel i. |
| 1 | A bit set at position i in the field RE indicates that no Reserved Short Packet interrupt is pending for virtual channel i. This bit is reset after the register read operation. |
Bits 15:12 – LE[3:0] Line End Interrupt Status
| Value | Description |
|---|---|
| 0 | A bit cleared at position i in the field LE indicates that no Line End interrupt is pending for virtual channel i. |
| 1 | A bit set at position i in the field LE indicates that a Line End interrupt is pending for virtual channel i. This bit is reset after the register read operation. |
Bits 11:8 – LS[3:0] Line Start Interrupt Status
| Value | Description |
|---|---|
| 0 | A bit cleared at position i in the field LS indicates that no Line Start interrupt is pending for virtual channel i. |
| 1 | A bit set at position i in the field LS indicates that a Line Start interrupt is pending for virtual channel i. This bit is reset after the register read operation. |
Bits 7:4 – FE[3:0] Frame End Interrupt Status
| Value | Description |
|---|---|
| 0 | A bit cleared at position i in the field FE indicates that no Frame End interrupt is pending for virtual channel i. |
| 1 | A bit set at position i in the field FE indicates that a Frame End interrupt is pending for virtual channel i. This bit is reset after the register read operation. |
Bits 3:0 – FS[3:0] Frame Start Interrupt Status
| Value | Description |
|---|---|
| 0 | A bit cleared at position i in the field FS indicates that no Frame Start interrupt is pending for virtual channel i. |
| 1 | A bit set at position i in the field FS indicates that a Frame Start interrupt is pending for virtual channel i. This bit is reset after the register read operation. |