5.7.6.36 CSI2DC IDS Interrupt Status Register
| Name: | CSI2DC_IDSISR |
| Offset: | 0x9C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVF | IDS[3:0] | ||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 4 – OVF Image Data Snoop Overflow Interrupt Status
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Indicates that the IDS controller captured more than 4 entries. This bit is reset after the register read operation. |
Bits 3:0 – IDS[3:0] Image Data Snoop Interrupt Status
| Value | Description |
|---|---|
| 0 | A bit cleared at position i in the field IDS indicates that no Image Data Snoop interrupt is pending for virtual channel i. |
| 1 | A bit set at position i in the field IDS indicates that a new Image Data Snoop entry interrupt is pending for table entry i. This bit is reset after the register read operation. |