5.2.6.1.1 Pixel Clock Period Configuration

The pixel clock (LCDC_PCK) generated by the timing engine is the source clock divided by the field CLKDIV in the Configuration register 0 (LCDC_LCDCFG0). The source clock is the GCLK clock.

The pixel clock period formula is:

LCDC_PCK = source clock CLKDIV + 2

To obtain LCDC_PCK = source clock, the clock divider can be disabled by configuring LCDC_LCDCFG0.CLKBYP.

The pixel clock polarity can be programmed in LCDC_LCDCFG0.CLKPOL.