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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
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SAM9X70
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SAM9X75
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3
Memories
3.7
OTP Memory Controller (OTPC)
3.7.5
Functional Description
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
3.1
Overview
3.2
External Bus Interface (EBI)
3.3
Static Memory Controller (SMC)
3.4
Programmable Multibit Error Correction Code Controller (PMECC)
3.5
Programmable Multibit ECC Error Location Controller (PMERRLOC)
3.6
DDR-SDRAM Controller (MPDDRC)
3.7
OTP Memory Controller (OTPC)
3.7.1
Description
3.7.2
Embedded Characteristics
3.7.3
Block Diagram
3.7.4
Product Dependencies
3.7.5
Functional Description
3.7.5.1
Bus Interfaces
3.7.5.2
OTP Memory Partitioning
3.7.5.3
User Area
3.7.5.4
OTP Emulation Mode
3.7.5.5
Interrupts
3.7.5.6
Register Write Protection
3.7.6
Register Summary
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
3.7.5 Functional Description
