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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
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3
Memories
3.3
Static Memory Controller (SMC)
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
3.1
Overview
3.2
External Bus Interface (EBI)
3.3
Static Memory Controller (SMC)
3.3.1
Description
3.3.2
Embedded Characteristics
3.3.3
I/O Lines Description
3.3.4
Interrupt Source
3.3.5
Multiplexed Signals
3.3.6
Application Example
3.3.7
Product Dependencies
3.3.8
External Memory Mapping
3.3.9
Connection to External Devices
3.3.10
Standard Read and Write Protocols
3.3.11
Automatic Wait States
3.3.12
Data Float Wait States
3.3.13
External Wait
3.3.14
Slow Clock Mode
3.3.15
Asynchronous Page Mode
3.3.16
Register Write Protection
3.3.17
Security and Safety Analysis and Reports
3.3.18
Scrambling/Unscrambling Function
3.3.19
Clearing Scrambling Keys on a Tamper Event
3.3.20
Register Summary
3.4
Programmable Multibit Error Correction Code Controller (PMECC)
3.5
Programmable Multibit ECC Error Location Controller (PMERRLOC)
3.6
DDR-SDRAM Controller (MPDDRC)
3.7
OTP Memory Controller (OTPC)
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
3.3 Static Memory Controller (SMC)
