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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
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7
Security and Cryptography Subsystem
7.2
Advanced Encryption Standard (AES)
7.2.4
Functional Description
7.2.4.4
Galois/Counter Mode (GCM)
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
7.1
Overview
7.2
Advanced Encryption Standard (AES)
7.2.1
Description
7.2.2
Embedded Characteristics
7.2.3
Product Dependencies
7.2.4
Functional Description
7.2.4.1
AES Register Endianness
7.2.4.2
Operating Modes
7.2.4.3
Last Output Data Mode (CBC-MAC)
7.2.4.4
Galois/Counter Mode (GCM)
7.2.4.4.1
Description
7.2.4.4.2
Key Writing and Automatic Hash Subkey Calculation
7.2.4.4.3
GCM Processing
7.2.4.5
XEX-based Tweaked-codebook Mode (XTS)
7.2.4.6
Double Input Buffer
7.2.4.7
Temporary Secured Storage for Keys
7.2.4.8
Start Modes
7.2.4.9
Automatic Padding Mode
7.2.4.10
Secure Protocol Layers Improved Performances
7.2.4.11
Security Features
7.2.5
Register Summary
7.3
Secure Hash Algorithm (SHA)
7.4
Triple Data Encryption Standard (TDES)
7.5
Random Number Generator (TRNG)
7.6
Physical Unclonable Functions (PUF)
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
7.2.4.4 Galois/Counter Mode (GCM)
