3.6.2 Embedded Characteristics

  • Supported Memory Devices:
    • DDR2-SDRAM
    • DDR3-SDRAM (DLL Off/On mode)
    • DDR3L-SDRAM (DLL Off/On mode)
  • Arbitration Policies: Round-Robin, On Request, Bandwidth, Quality of Service
  • Microchip Technology Non-Blocking Bus Interface Improves Quality of Service
  • Multiple Outstanding Bus Transactions Increase Bandwidth (up to 30 %)
  • 7 System Bus Interfaces; Management of all Accesses Maximizes Memory Bandwidth and Minimizes Transaction Latency
  • Bus Transfer: Word, Half Word, Byte Access
  • Supported Configurations:
    • 2K, 4K, 8K, 16K row address memory parts
    • DDR-SDRAM with four or eight internal banks (DDR2-SDRAM/DDR3-SDRAM/DDR3L-SDRAM)
    • DDR-SDRAM with 16-bit data path for system-oriented word access
    • One chip select for SDRAM device (256-Mbyte address space)
  • Programming Facilities
    • Multibank ping-pong access (up to four or eight banks opened at the same time = reduced average latency of transactions)
    • Timing parameters specified by software
    • Automatic refresh operation, refresh rate is programmable
  • Energy-Saving Capabilities
    • Self-Refresh, Power-Down and Active Power-Down modes supported
  • DDR-SDRAM Power-Up Initialization by Software
  • CAS Latency of 3, 4, 5 or 6 Supported
  • Reset Function Supported (DDR2-SDRAM)
  • Clock Frequency Change in Self-Refresh Mode Supported (/DDR2-SDRAM/DDR3-SDRAM/DDR3L-SDRAM)
  • Auto-precharge Command Not Used
  • OCD (Off-chip Driver) Mode, ODT (On-die Termination), Write leveling are Not Supported
  • Abnormal Software Access and Sequencer Integrity Error Reports
  • Dynamic Scrambling with User Key (No Impact on Bandwidth)
  • Bus Monitor