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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
Product Pages
SAM9X70 SAM9X72 SAM9X75
  1. Home
  2. 4 System Controller
  3. 4.13 Debug Unit (DBGU)
  4. 4.13.5 Functional Description
  5. 4.13.5.5 Register Write Protection

  • Introduction
  • Reference Document
  • 1 Overview
  • 2 CPU and Interconnect
  • 3 Memories
  • 4 System Controller
    • 4.1 Overview
    • 4.2 System Controller Write Protection (SYSCWP)
    • 4.3 Advanced Interrupt Controller (AIC)
    • 4.4 Boot Sequence Controller (BSC)
    • 4.5 General Purpose Backup Registers (GPBR)
    • 4.6 Watchdog Timer (WDT)
    • 4.7 Reset Controller (RSTC)
    • 4.8 Real-Time Timer (RTT)
    • 4.9 Real-Time Clock (RTC)
    • 4.10 Shutdown Controller (SHDWC)
    • 4.11 Periodic Interval Timer (PIT)
    • 4.12 64-bit Periodic Interval Timer (PIT64B)
    • 4.13 Debug Unit (DBGU)
      • 4.13.1 Description
      • 4.13.2 Embedded Characteristics
      • 4.13.3 Block Diagram
      • 4.13.4 Product Dependencies
      • 4.13.5 Functional Description
        • 4.13.5.1 Baud Rate Generator
        • 4.13.5.2 Receiver
        • 4.13.5.3 Transmitter
        • 4.13.5.4 DMA Support
        • 4.13.5.5 Register Write Protection
        • 4.13.5.6 Test Modes
        • 4.13.5.7 Debug Communication Channel Support
        • 4.13.5.8 Chip Identifier
        • 4.13.5.9 ICE Access Prevention
      • 4.13.6 Register Summary
    • 4.14 Special Function Registers (SFR)
    • 4.15 Slow Clock Controller (SCKC)
    • 4.16 Clock Generator
    • 4.17 Power Management Controller (PMC)
    • 4.18 Parallel Input/Output Controller (PIO)
  • 5 Image Subsystem
  • 6 Audio Subsystem
  • 7 Security and Cryptography Subsystem
  • 8 Connectivity Subsystem
  • 9 USB Subsystem
  • 10 Electrical and Mechanical Characteristics
  • 11 Revision History
  • Microchip Information

4.13.5.5 Register Write Protection

To prevent any single software error from corrupting DBGU behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the DBGU Write Protection Mode Register.

The following registers can be write-protected:

  • DBGU Mode Register
  • DBGU Baud Rate Generator Register
  • DBGU Receiver Timeout Register
  • Debug Unit Force NTRST Register

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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