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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
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8
Connectivity Subsystem
8.3
Flexible Serial Communication Controller (FLEXCOM)
8.3.8
SPI Functional Description
8.3.8.3
Host Mode Operations
8.3.8.3.1
Host Mode Block Diagram
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
8.1
Overview
8.2
Ethernet MAC (GMAC)
8.3
Flexible Serial Communication Controller (FLEXCOM)
8.3.1
Description
8.3.2
Embedded Characteristics
8.3.3
Block Diagram
8.3.4
I/O Lines Description
8.3.5
Product Dependencies
8.3.6
Register Accesses
8.3.7
USART Functional Description
8.3.8
SPI Functional Description
8.3.8.1
Modes of Operation
8.3.8.2
Data Transfer
8.3.8.3
Host Mode Operations
8.3.8.3.1
Host Mode Block Diagram
8.3.8.3.2
Host Mode Flowchart
8.3.8.3.3
Clock Generation
8.3.8.3.4
Transfer Delays
8.3.8.3.5
Peripheral Selection
8.3.8.3.6
SPI Direct Access Memory Controller (DMAC)
8.3.8.3.7
Peripheral Chip Select Decoding
8.3.8.3.8
Peripheral Deselection without
DMA
8.3.8.3.9
Peripheral Deselection with
DMA
8.3.8.3.10
Mode Fault Detection
8.3.8.4
SPI Client Mode
8.3.8.5
SPI Comparison Function on Received Character
8.3.8.6
SPI FIFOs
8.3.8.7
SPI CRC Generation and Checking
8.3.8.8
Two-Pin Mode
8.3.8.9
SPI Register Write Protection
8.3.8.10
Local Loopback Test Mode
8.3.9
TWI Functional Description
8.3.10
Register Summary
8.4
Quad Serial Peripheral Interface (QSPI)
8.5
Secure Digital MultiMedia Card Controller (SDMMC)
8.6
Controller Area Network (MCAN)
8.7
Timer Counter (TC)
8.8
Pulse Width Modulation Controller (PWM)
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
8.3.8.3.1 Host Mode Block Diagram
Figure 8-87.
Host Mode Block Diagram
