6.3.7.10 I2SMCC Interrupt Disable Register B

This register can only be written if WPITEN is cleared in the Inter-IC Sound Write Protection Mode Register.

The following configuration values are valid for the listed bit of this register:

0: No effect.

1: Disables the corresponding interrupt.

Name: I2SMCC_IDRB
Offset: 0x24
Reset: –
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
        WERR 
Access W 
Reset – 

Bit 0 – WERR Write Error Interrupt Disable