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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
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8
Connectivity Subsystem
8.2
Ethernet MAC (GMAC)
8.2.6
Functional Description
8.2.6.5
Transmit Scheduling Algorithm
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
8.1
Overview
8.2
Ethernet MAC (GMAC)
8.2.1
Description
8.2.2
Embedded Characteristics
8.2.3
Block Diagram
8.2.4
Signal Interfaces
8.2.5
Product Dependencies
8.2.6
Functional Description
8.2.6.1
Media Access Controller
8.2.6.2
1588 Timestamp Unit
8.2.6.3
Direct Memory Access Interface
8.2.6.4
MAC Transmit Block
8.2.6.5
Transmit Scheduling Algorithm
8.2.6.5.1
Introduction
8.2.6.5.2
802.1Qav Support - Credit-based Shaping
8.2.6.5.3
Fixed Priority
8.2.6.5.4
Deficit Weighted Round Robin (DWRR)
8.2.6.5.5
Enhanced Transmission Selection (ETS)
8.2.6.5.6
Enhancement for Scheduled Traffic (EnST)
8.2.6.6
MAC Receive Block
8.2.6.7
Checksum Offload for IP, TCP and UDP
8.2.6.8
MAC Filtering Block
8.2.6.9
Broadcast Address
8.2.6.10
Hash Addressing
8.2.6.11
Copy all Frames (Promiscuous Mode)
8.2.6.12
Disable Copy of Pause Frames
8.2.6.13
VLAN Support
8.2.6.14
Wake on LAN Support
8.2.6.15
IEEE 1588 Support
8.2.6.16
MAC 802.3 Pause Frame Support
8.2.6.17
MAC PFC Priority-based Pause Frame Support
8.2.6.18
Energy-efficient Ethernet Support
8.2.6.19
LPI Operation in the GMAC
8.2.6.20
PHY Interface
8.2.6.21
10/100 Operation
8.2.6.22
Jumbo Frames
8.2.6.23
Time-sensitive Networking Support (TSN)
8.2.7
Programming Interface
8.2
Register Summary
8.3
Flexible Serial Communication Controller (FLEXCOM)
8.4
Quad Serial Peripheral Interface (QSPI)
8.5
Secure Digital MultiMedia Card Controller (SDMMC)
8.6
Controller Area Network (MCAN)
8.7
Timer Counter (TC)
8.8
Pulse Width Modulation Controller (PWM)
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
8.2.6.5 Transmit Scheduling Algorithm
