7.3.7.8 I2SMCC Interrupt Status Register A

Name:	I2SMCC_ISRA
Offset:	0x1C
Reset:	0x00000003
Property:	Read-only


Bit	31	30	29	28	27	26	25	24
							RXROVF0	RXLOVF0
Access							R	R
Reset							0	0


Bit	23	22	21	20	19	18	17	16
							RXRRDY0	RXLRDY0
Access							R	R
Reset							0	0


Bit	15	14	13	12	11	10	9	8
							TXRUNF0	TXLUNF0
Access							R	R
Reset							0	0


Bit	7	6	5	4	3	2	1	0
							TXRRDY0	TXLRDY0
Access							R	R
Reset							1	1

Bit 25 – RXROVFx I²S Receive Right x (x=0 only) or TDM Channel [2x]+1 Overrun Flag (cleared on read)

Value	Description
0	Cleared when I2SMCC_ISRA is read.
1	Set when an overrun error occurs in I2SMCC_RHR.

Bit 24 – RXLOVFx I²S Receive Left x (x=0 only) or TDM Channel 2x Overrun Flag (cleared on read)

Value	Description
0	Cleared when I2SMCC_ISRA is read.
1	Set when an overrun error occurs in I2SMCC_RHR.

Bit 17 – RXRRDYx I²S Receive Right x (x=0 only) or TDM Channel [2x]+1 Ready Flag (cleared by reading I2SMCC_RHR)

Value	Description
0	Cleared when a predefined number of read accesses are performed in I2SMCC_RHR. The predefined number depends on the configuration of I2SMCC_MRA.WIRECFG / FORMAT and varies from 1 to 8.
1	Set when received data is available in I2SMCC_RHR.

Bit 16 – RXLRDYx I²S Receive Left x (x=0 only) or TDM Channel 2x Ready Flag (cleared by reading I2SMCC_RHR)

Value	Description
0	Cleared when a predefined number of read accesses is performed in I2SMCC_RHR. The predefined number depends on the configuration of I2SMCC_MRA.WIRECFG/FORMAT and varies from 1 to 7.
1	Set when received data is available in I2SMCC_RHR.

Bit 9 – TXRUNFx I²S Transmit Right x (x=0 only) or TDM Channel [2x]+1 Underrun Flag (cleared on read)

Value	Description
0	Cleared when the I2SMCC_ISRA is read.
1	Set when an underrun error occurs in I2SMCC_THR.

Bit 8 – TXLUNFx I²S Transmit Left x (x=0 only) or TDM Channel 2x Underrun (cleared on read)

Value	Description
0	Cleared when I2SMCC_ISRA is read.
1	Set when an underrun error occurs in I2SMCC_THR.

Bit 1 – TXRRDYx I²S Transmit Right x (x=0 only) or TDM Channel [2x]+1 Ready Flag (cleared by writing I2SMCC_THR)

Value	Description
0	Cleared when a predefined number of write accesses is performed in I2SMCC_THR. The predefined number depends on the configuration of I2SMCC_MRA.WIRECFG/FORMAT and varies from 1 to 8.
1	Set when I2SMCC_THR is empty.

Bit 0 – TXLRDYx I²S Transmit Left x (x=0 only) or TDM Channel 2x Ready Flag (cleared by writing I2SMCC_THR)

Value	Description
0	Cleared when a predefined number of write accesses is performed in I2SMCC_THR. The predefined number depends on the configuration of I2SMCC_MRA.WIRECFG/FORMAT and varies from 1 to 7.
1	Set when I2SMCC_THR is empty.

DS60001813E

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