7.3.7.6 I2SMCC Interrupt Disable Register A

This register can only be written if WPITEN is cleared in the Inter-IC Sound Write Protection Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Disables the corresponding interrupt.

Name:	I2SMCC_IDRA
Offset:	0x14
Reset:	–
Property:	Write-only


Bit	31	30	29	28	27	26	25	24
							RXROVF0	RXLOVF0
Access							W	W
Reset							–	–


Bit	23	22	21	20	19	18	17	16
							RXRRDY0	RXLRDY0
Access							W	W
Reset							–	–


Bit	15	14	13	12	11	10	9	8
							TXRUNF0	TXLUNF0
Access							W	W
Reset							–	–


Bit	7	6	5	4	3	2	1	0
							TXRRDY0	TXLRDY0
Access							W	W
Reset							–	–

Bit 25 – RXROVFx I²S Receive Right x (x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Disable

Bit 24 – RXLOVFx I²S Receive Left x (x=0 only) or TDM Channel 2x Overrun Interrupt Disable

Bit 17 – RXRRDYx I²S Receive Right x (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Disable

Bit 16 – RXLRDYx I²S Receive Left x (x=0 only) or TDM Channel 2x Ready Interrupt Disable

Bit 9 – TXRUNFx I²S Transmit Right x (x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Disable

Bit 8 – TXLUNFx I²S Transmit Left x (x=0 only) or TDM Channel 2x Underrun Interrupt Disable

Bit 1 – TXRRDYx I²S Transmit Right x (x=0 only) or TDM Channel [2x]+1 Ready Interrupt Disable

Bit 0 – TXLRDYx I²S Transmit Left x (x=0 only) or TDM Channel 2x Ready Interrupt Disable

DS60001813E

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