The following configuration values are valid for all listed bit names of this
register:
0: The corresponding source of interrupt is disabled.
1: The corresponding source of interrupt is enabled.
Name:
I2SMCC_IMRA
Offset:
0x18
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
RXROVF0
RXLOVF0
Access
R
R
Reset
0
0
Bit
23
22
21
20
19
18
17
16
RXRRDY0
RXLRDY0
Access
R
R
Reset
0
0
Bit
15
14
13
12
11
10
9
8
TXRUNF0
TXLUNF0
Access
R
R
Reset
0
0
Bit
7
6
5
4
3
2
1
0
TXRRDY0
TXLRDY0
Access
R
R
Reset
0
0
Bit 25 – RXROVFx I2S Receive Right x
(x=0 only) or TDM Channel [2x]+1 Overrun Interrupt Mask
Bit 24 – RXLOVFx I2S Receive Left x (x=0
only) or TDM Channel 2x Overrun Interrupt Mask
Bit 17 – RXRRDYx I2S Receive Right x
(x=0 only) or TDM Channel [2x]+1 Ready Interrupt Mask
Bit 16 – RXLRDYx I2S Receive Left x (x=0
only) or TDM Channel 2x Ready Interrupt Mask
Bit 9 – TXRUNFx I2S Transmit Right x
(x=0 only) or TDM Channel [2x]+1 Underrun Interrupt Mask
Bit 8 – TXLUNFx I2S Transmit Left x
(x=0 only) or TDM Channel 2x Underrun Interrupt Mask
Bit 1 – TXRRDYx I2S Transmit Right x
(x=0 only) or TDM Channel [2x]+1 Ready Interrupt Mask
Bit 0 – TXLRDYx I2S Transmit Left x
(x=0 only) or TDM Channel 2x Ready Interrupt Mask
DS60001813E
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
