42.6.3 DMA Operation

The SLCD generates the following DMA requests:

  • Display Memory Update (DMU): the request is set when the selected frame counter overflows. To select the frame counter for DMA to update the display memory, write the frame counter index to Display Memory Frame Counter Selection bits in the Control A register (CTRLA.DMFCS).

    The request is cleared when any SDATAL/Hx register is written to. Refer to 42.6.2.1 Frame Counters for details.
 The frame counter associated to the DMA request is the same as the interrupt source, refer also to 42.6.4 Interrupts.

  • Automated Character Mapping Data Ready (ACMDRDY): the request is set when the frame counter associated to automated character mapping function overflows. The request is cleared when CMDATA register is written. Refer to 42.6.2.6 Automated Character Mapping for details.
  • Automated Bit Mapping Data Ready (ABMDRDY): the request is set when the frame counter associated to automated bit mapping function overflows. The request is cleared when ISDATA register is written. Refer to 42.6.2.7 Automated Bit Mapping for details.
Note: If the CPU accesses the registers which are source of DMA request set/clear condition, the DMA request can be lost or the DMA transfer can be corrupted, if enabled.