38.11 Device Endpoint Register Summary
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0xFF | Reserved | |||||||||
| 0x0100 | EPCFG0 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
| ... | ||||||||||
| 0x0104 | EPSTATUSCLR0 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| ... | ||||||||||
| 0x0105 | EPSTATUSSET0 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| ... | ||||||||||
| 0x0106 | EPSTATUS0 | 7:0 | BK1RDY | BK0RDY | STALLRQ | CURBK | DTGLIN | DTGLOUT | ||
| ... | ||||||||||
| 0x0107 | EPINTFLAG0 | 7:0 | STALL | RXSTP | TRFAIL | TRCPT | ||||
| ... | ||||||||||
| 0x0108 | EPINTENCLR0 | 7:0 | STALL | RXSTP | TRFAIL | TRCPT | ||||
| ... | ||||||||||
| 0x0109 | EPINTENSET0 | 7:0 | STALL | RXSTP | TRFAIL | TRCPT | ||||
| ... | ||||||||||
| 0x0114 | EPCFG20 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
| 0x0118 | EPSTATUSCLR20 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0119 | EPSTATUSSET20 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x011A | EPSTATUS20 | 7:0 | BK1RDY | BK0RDY | STALLRQ | CURBK | DTGLIN | DTGLOUT | ||
| 0x011B | EPINTFLAG20 | 7:0 | STALL | RXSTP | TRFAIL | TRCPT | ||||
| 0x011C | EPINTENCLR20 | 7:0 | STALL | RXSTP | TRFAIL | TRCPT | ||||
| 0x011D | EPINTENSET20 | 7:0 | STALL | RXSTP | TRFAIL | TRCPT | ||||