15.5 Debug and Test Pin Description
| Pin Name | Function | Type | Active Level |
|---|---|---|---|
| Reset/Test | |||
| NRST | Microprocessor Reset | Input | Low |
| TST | Test Mode Select | Input | – |
| NTRST | Test Reset Signal | Input | – |
| ICE and JTAG | |||
| TCK/SWCLK | Test Clock/Serial Wire Clock | Input | – |
| TDI | Test Data In | Input | – |
| TDO | Test Data Out | Output | – |
| TMS/SWDIO | Test Mode Select/Serial Wire Input/Output | I/O | – |
| JTAGSEL | JTAG Selection | Input | – |