Controls the Interrupt Lines (nIRQ and nFIQ) of an ARM Processor
128 Individually Maskable and Vectored
Interrupt Sources
Source 0 is reserved for the fast interrupt input (FIQ)
Source 74 is reserved for system peripheral
interrupts
Sources 2 to 73 and
Sources 75 to 127 control up to
125 embedded
peripheral interrupts or external interrupts
Programmable edge-triggered or level-sensitive internal
sources
Programmable rising/falling edge-triggered or high/low
level-sensitive external sources
8-level Priority Controller
Drives the normal interrupt of the processor
Handles priority of the interrupt sources 1 to 127
Higher priority interrupts can be served during service of lower priority interrupt
Vectoring
Optimizes interrupt service routine branch and execution
One 32-bit vector register for all interrupt sources
Interrupt vector register reads the corresponding current interrupt vector
Protect Mode
Easy debugging by preventing automatic operations when protect models are enabled
General Interrupt Mask
Provides processor synchronization on events without triggering an interrupt
Register Write Protection
AIC0 is Non-Secure AIC, AIC1 is Secure AIC
AIC0 manages nIRQ line, AIC1 manages nFIQ line
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
