4.1 MCP16502 PMIC

MCP16502 features four 1A DC-DC Buck regulators and two 0.3A auxiliary LDO regulators, and provides a comprehensive interface to the MPU, which includes an interrupt flag and a 1-MHz I²C interface. The PMIC processor interface is optimized so that it remains leakage-free in any power mode, in particular, Backup mode or BSR mode. MCP16502’s VOUT2 voltage, corresponding to VDDIODDR, is pin-selectable from 1.2V, 1.35V or 1.8V to cover all supported SDRAM memory types. The application's primary rails (3.3V, 1.25V and VDDIODDR) are all fed from DC-DC converters for maximum efficiency.

Two versions of the MCP16502 are available:
  • MCP16502AA supports SAMA5D2 systems with CPU frequency up to 500 MHz and using LPSDR-, LPDDR- or DDR2-SDRAM memories (1.8V), or DDR3L-SDRAM memories (1.35V)
  • MCP16502AC supports SAMA5D2 systems with CPU frequency up to 500 MHz using LPDDR2- or LPDDR3-SDRAM (1.2V and 1.8V). In this case, VOUT2 is set to 1.2V through SELV2 pin level and LOUT1 to 1.8V through SELV1 pin level.

The figure below gives an application schematic example of a SAMA5D2 with DDR3L-SDRAM system running at a CPU frequency up to 500 MHz, powered by MCP16502AA. The fourth DC-DC converter of MCP16502AA is OFF by default during start-up and its components may be removed. The two LDO regulator outputs LOUT1 and LOUT2 are auxiliary power rails available for the application. LOUT1 output is ON by default at power-up and its default voltage is set to 2.5V, with the SELV1 pin connection, to power VDDFUSE input of SAMA5D2. When VDDFUSE is not needed in the application, LOUT1 can be repurposed. LOUT2, OFF by default at power-up, can be started by software through the I²C control bus to the necessary voltage. The BSR low-power mode of the processor is entered and exited by a combination of the PIOBU0 and the SHDN pins of the processor.

For further details, refer to the MCP16502 documentation on www.microchip.com.

Figure 4-1. Application Schematic Example with MCP16502AA