13.5.2 Processor Operating States

The processor has the following instruction set states controlled by the T bit and J bit in the CPSR.

• ARM state:

  The processor executes 32-bit, word-aligned ARM instructions.

• Thumb-2 state:

  The processor executes 16-bit and 32-bit, halfword-aligned Thumb-2 instructions.

• Thumb-2EE state:

  The processor executes a variant of the Thumb-2 instruction set designed as a target for dynamically generated code. This is code compiled on the device either shortly before or during execution from a portable bytecode or other intermediate or native representation.

• Jazelle state:

  The processor executes variable length, byte-aligned Java bytecodes.

The J bit and the T bit determine the instruction set used by the processor. The table below shows the encoding of these bits.

Alternating between ARM and Thumb-2 states does not affect the processor mode or the register contents. See the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition for information on entering and exiting Thumb-2EE state.