37.4 DMA Controller Peripheral Connections

The SAMA5D2 features two DMACs: XDMAC0 and XDMAC1. Both have the same features:

• Programmable secure access
• Two 64-bit hosts
• 16 channels and 55 hardware requests embedded
• Sixteen 64-bit-word FIFOs on all channels
• Linked list support with status write back operation at end of transfer
• Word, half-word, byte transfer support
• Memory-to-memory transfer
• Peripheral-to-memory transfer
• Memory-to-peripheral transfer

The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the peripherals below.

The following table gives an overview of the different access when secure/non-secure DMA needs to access a secure/non-secure peripheral, and when a secure/non-secure peripheral needs to access secure/non-secure DMA.

DMA Controller 0 manages transfers between peripherals and memory, and receives the triggers from the peripherals listed in the following table.

DMA Controller 1 manages transfers between peripherals and memory, and receives the triggers from the peripherals listed in the following table.