64.5.5.2 BUREG256b Erase Sequence
In parallel to the BUSRAM4KB erase, the BUREG256b register bank is immediately cleared (zero clock cycle).
BUREG256b reads ‘0’ after a VDDBU power-up or an erase event.
In parallel to the BUSRAM4KB erase, the BUREG256b register bank is immediately cleared (zero clock cycle).
BUREG256b reads ‘0’ after a VDDBU power-up or an erase event.
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