49.7.9 QSPI Serial Clock Register
This register can only be written if bit WPEN is cleared in the QSPI Write Protection Mode Register.
| Name: | QSPI_SCR |
| Offset: | 0x20 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DLYBS[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SCBR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CPHA | CPOL | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bits 23:16 – DLYBS[7:0] Delay Before QSCK
This field defines the delay from QCS valid to the first valid QSCK transition.
When DLYBS equals zero, the QCS valid to QSCK transition is 1/2 the QSCK clock period.
Otherwise, the following equation determines the delay:
DLYBS = Delay Before QSCK × fperipheral clock
Bits 15:8 – SCBR[7:0] Serial Clock Baud Rate
The QSPI uses a modulus counter to derive the QSCK baud rate from the peripheral clock. The baud rate is selected by writing a value from 0 to 255 in the SCBR field. The following equation determines the QSCK baud rate:
SCBR = (fperipheral clock / QSCK Baudrate) - 1
Bit 1 – CPHA Clock Phase
CPHA determines which edge of QSCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between host and client devices.
| Value | Description |
|---|---|
| 0 | Data is captured on the leading edge of QSCK and changed on the following edge of QSCK. |
| 1 | Data is changed on the leading edge of QSCK and captured on the following edge of QSCK (only available in SPI mode, QSPI_MR.SMM=0). |
Bit 0 – CPOL Clock Polarity
CPOL is used to determine the inactive state value of the serial clock (QSCK). It is used with CPHA to produce the required clock/data relationship between host and client devices.
| Value | Description |
|---|---|
| 0 | The inactive state value of QSCK is logic level zero. |
| 1 | The inactive state value of QSCK is logic level one (only available in SPI mode, QSPI_MR.SMM=0). |