37.2.4.4 Transmit and Receive Buffers and FIFO
This Target module contains separate independent Transmit and Receive Buffers, which the
user software can interact with to send data to and receive data from the Target. The
user can write to I3CxTXB Transmit Buffer Register to send data onto the bus. The I3CxRXB
Receive Buffer Register contains data the Target receives from the Controller that the
user can read. The Transmit and Receive Buffers are each equipped with separate
dedicated FIFOs. Both the Transmit and Receive FIFOs on this Target module are 8 bytes each. The user can only send and
receive data through the I3CxTXB Transmit and I3CxRXB Receive Buffers, the Transmit and
Receive FIFOs are not user accessible. The CLRTXB
and CLRRXB bits can be used to clear the Transmit and Receive Buffers and
FIFOs.
Refer to the Interrupts and DMA Triggers section for more information on the different interrupts and DMA triggers mentioned in this section and how to use them.
Tip: It is recommended that the user use DMA to read and
write from the I3C Transmit and Receive Buffers to ensure that the CPU can keep up with
the higher I3C speeds. Refer to the Interrupts and DMA Triggers
section and “DMA - Direct Memory Access” chapter for more information.