37.4.1 I3CxCON0

Note:
  1. Self-clears after Software Reset is complete.
  2. Self-clears when the corresponding buffer and FIFO reset operation is complete.
  3. The normal behavior of ACKP can be temporarily altered by the ACKPOS bit.
  4. Self-clears when either DACHIF or HJEIF bit is set by the hardware. Behavior may be temporarily altered by the status of the HJEN bit.
  5. Self-clears when either IBIDONEIF or IBIEIF bit is set by the hardware. Behavior may be temporarily altered by the status of the IBIEN bit.
  6. In case of a race condition, user writes always take precedence over hardware events.
Name: I3CxCON0
Address: 0x083, 0x0B6

Control 0

Bit 76543210 
 ENBTOENRSTCLRTXBCLRRXBACKPHJREQIBIREQ 
Access R/WR/WR/W/HCR/W/HCR/W/HCR/WR/W/HCR/W/HC 
Reset 00000000 

Bit 7 – EN  Target Enable

ValueDescription
1 Enable the Target interface
0 Disable the Target interface

Bit 6 – BTOEN  Bus Time-out Enable

ValueDescription
1 Bus Time-out counter (I3CxBTO) is enabled
0 Bus Time-out counter (I3CxBTO) is disabled

Bit 5 – RST  Software Reset(1)

ValueDescription
1 Initiate a software Reset of the module
0 A software module Reset has not been initiated or was completed

Bit 4 – CLRTXB  Clear Transmit Buffer and FIFO(2)

ValueDescription
1 Initiate a Reset of the I3CxTXB Transmit Buffer and Transmit FIFO
0 A Read FIFO and I3CxTXB Transmit Buffer Reset has not been initiated or was completed

Bit 3 – CLRRXB  Clear Receive Buffer and FIFO(2)

ValueDescription
1 Initiate a Reset of the I3CxRXB Receive Buffer and Receive FIFO
0 A Read FIFO and I3CxRXB Receive Buffer Reset has not been initiated or was completed

Bit 2 – ACKP  Private Transaction Acknowledge(3)

ValueDescription
1 Private/I2C Write/Read requests are normally NACK'd
0 Private/I2C Write/Read requests are normally ACK'd

Bit 1 – HJREQ  Hot-Join Request(4)

ValueNameDescription
X HJCAP = 0 This bit is ignored
1 HJCAP = 1 Initiate a Hot-Join Request to the Controller upon next Start or Bus Idle condition
0 HJCAP = 1 A Hot-Join Request has not been initiated or was completed

Bit 0 – IBIREQ  In-Band Interrupt Request(5)

ValueDescription
1 Initiate an In-Band Interrupt Request to the Controller upon next Start or Bus Available condition
0 An In-Band Interrupt Request has not been initiated or was completed
Self-clears after Software Reset is complete. Self-clears when the corresponding buffer and FIFO reset operation is complete. The normal behavior of ACKP can be temporarily altered by the ACKPOS Private Transaction Acknowledge One-shot(***) bit. Self-clears when either DACHIF Dynamic Address Changed Interrupt Flag(***) or HJEIF Hot-Join Error Interrupt Flag(1) bit is set by the hardware. Behavior may be temporarily altered by the status of the HJEN Hot-Join Requests Status bit. Self-clears when either IBIDONEIF In-Band Interrupt Done Interrupt Flag(1) or IBIEIF In-Band Interrupt Error Flag(***) bit is set by the hardware. Behavior may be temporarily altered by the status of the IBIEN In-Band Interrupt Requests Status bit. In case of a race condition, user writes always take precedence over hardware events.