37.2.11.3 Levels of Target Reset
Through the RSTACT CCC, there are three levels of reset that the Controller can configure the Target to perform upon receiving the Target Reset Pattern:
- No Target Reset.
- Reset the I3C Target module only.
- Reset the entire Target device.
The specific reset level is identified by the Defining Byte that is sent along with the Direct or Broadcast Write RSTACT CCC. The defining byte is stored in the I3CxRSTACT register. Refer to Table 37-14 in the definition of RSTACT CCC for a list of available configuration options.
The I3CxRSTACT register is initialized to 0xFF
upon module reset. Once
the Target receives the RSTACT CCC, the I3CxRSTACT register is updated with the defining
byte of the RSTACT CCC, which allows the user software to configure the Target for the
appropriate reset action.
0xFF
to it.When the Target receives a Target Reset Pattern immediately following the RSTACT CCC, the user software is expected to perform the configured reset action based on the I3CxRSTACT Defining Byte values as mentioned in Table 37-15.
Refer to Pseudo-code for Target Reset Pattern Detection to learn more about using user software in conjunction with the different levels of Target reset actions.
I3CxRSTACT Defining Byte | Level of Reset | Recommended User Action |
---|---|---|
0x00 |
No Target Reset | Nothing, No reset action to be performed |
0x01 |
Reset I3C Target Module | Perform a software reset of the Target module as outlined in Software Target Reset |
0x02 |
Reset Entire Target Device | Perform a system level reset of the entire device. Refer to the
“RESET Instruction” section in the
“Resets” chapter. |
Pseudo-code for Target Reset Pattern Detection
// Counter to count number of non-RSTACT reset patterns uint8_t count = 0; inline void I3C1_Target_SoftwareReset() { // Perform software reset I3C1CON0bits.RST = 1; // Wait for software reset to complete while(I3C1CON0bits.RST); // RST bit clears upon reset completion } void I3C1_Target_Reset_ISR() { // This ISR is executed when PIRx.I3C1RIF is set // Target Reset Pattern detected on bus // First, clear the flag to re-arm PIRxbits.I3C1RIF = 0; // x = appropriate PIR register // Check status of RSTACT CCC Defining Byte // RSTACT DB 0x00 ==> No reset // RSTACT DB 0x01 ==> I3C peripheral reset // RSTACT DB 0x02 ==> Whole chip reset if(I3C1RSTACT == 0x00) { // Reset counter and do nothing count = 0; } else if(I3C1RSTACT == 0x01) { // Suggested user action is to reset the I3C module count = 0; // Reset counter I3C1_Target_SoftwareReset(); } else if(I3C1RSTACT == 0x02) { // Suggested user action is to reset the entire device count = 0; // Reset counter RESET(); } else if(I3C1RSTACT == 0xFF) { // Target Reset Pattern detected without any preceeding RSTACT CCC if(count == 0) { // Reset Pattern detected w/o RSTACT for the first time // Suggested user action is to reset the I3C module count++; // Increment counter I3C1_Target_SoftwareReset(); } else if(count > 0) { // Reset Pattern detected w/o RSTACT for the second time // Suggested user action is to reset the whole device // Note that the counter can be reset by user software if GETSTATUS CCC is received count = 0; // Reset counter RESET(); } } // Reset RSTACT CCC Defining Byte to default value for future detection I3C1RSTACT = 0xFF; }