7.1.2 Device is Awake

When the device is awake, it honors the conditions listed below:

DATA Zero: If SDA is low and stable while SCL goes from low to high to low, then a zero bit is being transferred on the bus. SDA can change while SCL is low.
DATA One: If SDA is high and stable while SCL goes from low to high to low, then a one bit is being transferred on the bus. SDA can change while SCL is low.
Figure 7-1. Data Bit Transfer on I²C Interface
Start Condition: A high-to-low transition of SDA with SCL high is a Start condition which must precede all commands.
Stop Condition: A low-to-high transition of SDA with SCL high is a Stop condition. After this condition is received by the device, the current I/O transaction ends. On input, if the device has sufficient bytes to execute a command, the device transitions to the busy state and begins execution. The Stop condition must always be sent at the end of any packet sent to the device.
Figure 7-2. Start and Stop Conditions on I²C Interface
Acknowledge (ACK): On the ninth clock cycle after every address or data byte is transferred, the receiver will pull the SDA pin low to acknowledge proper reception of the byte.
Not Acknowledge (NACK): Alternatively, on the ninth clock cycle after every address or data byte is transferred, the receiver can leave the SDA pin high to indicate that there was a problem with the reception of the byte or that this byte completes the group transfer.
Figure 7-3. NACK and ACK Conditions on I²C Interface

Multiple ATECC608B-TNGTLS devices can easily share the same I²C interface signals if the I2C_Address byte in the Configuration zone is programmed differently for each device on the bus. Because all seven of the bits of the device address are programmable, ATECC608B-TNGTLS can also share the I²C interface with any I²C device, including any Serial EEPROM.