6 Appendix B

This section provides information about the device IDs and pinout descriptions.

Table 6-1. Programming Pin Locations by Package Type
Device Package Package Code VDD VDDIO2 VSS MCLR ICSPCLK ICSPDAT
PIN PIN PIN PIN PORT PIN PORT PIN PORT

PIC18F24Q24
PIC18F25Q24
PIC18F26Q24

28-Pin SPDIP (SP) 20 18 19, 8 1 RE3 27 RB6 28 RB7
28-Pin SOIC (SO) 20 18 19, 8 1 RE3 27 RB6 28 RB7
28-Pin SSOP (SS) 20 18 19, 8 1 RE3 27 RB6 28 RB7
28-Pin VQFN (STX) 17 15 16, 5 26 RE3 24 RB6 25 RB7

PIC18F45Q24
PIC18F46Q24

40-Pin PDIP (P) 32, 11 26 31, 12 1 RE3 39 RB6 40 RB7
40-Pin VQFN (MP) 26, 7 1 27, 6 16 RE3 14 RB6 15 RB7
44-Pin TQFP (PT) 28, 7 1 29, 6 18 RE3 16 RB6 17 RB7

PIC18F55Q24
PIC18F56Q24

48-Pin VQFN (6LX) 30, 7 1 31 , 6 20 RE3 18 RB6 19 RB7
48-Pin TQFP (PT) 30, 7 1 31, 6 20 RE3 18 RB6 19 RB7
Note:

The most current package drawings are located in the Microchip Packaging Specification, DS00000049 (http://www.microchip.com/packaging). The drawing numbers listed above do not include the current revision designator, which is added at the end of the number.