6.5 CONFIG5
| Name: | CONFIG5 |
| Offset: | 30 0004h |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WDTE[1:0] | WDTCPS[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | ||
Bits 6:5 – WDTE[1:0] WDT Operating Mode
| Value | Description |
|---|---|
| 11 | WDT enabled regardless of Sleep; SEN bit in WDTCON0 is ignored |
| 10 | WDT enabled
while Sleep = 0, suspended when Sleep = 1; SEN
bit in WDTCON0 is ignored |
| 01 | WDT enabled/disabled by SEN bit in WDTCON0 |
| 00 | WDT disabled, SEN bit in WDTCON0 is ignored |
Bits 4:0 – WDTCPS[4:0] WDT Period Select
| WDTCPS | WDTCON0[WDTPS] at POR | Software Control of WDTPS? | |||
|---|---|---|---|---|---|
| Value | Divider Ratio | Typical Time Out (FIN = 31 kHz) |
|||
11111 |
01011 |
1:65536 | 216 | 2s | Yes |
11110 to 10011 |
11110 to 10011 |
1:32 | 25 | 1 ms | No |
10010 |
10010 |
1:8388608 | 223 | 256s | No |
10001 |
10001 |
1:4194304 | 222 | 128s | No |
10000 |
10000 |
1:2097152 | 221 | 64s | No |
01111 |
01111 |
1:1048576 | 220 | 32s | No |
01110 |
01110 |
1:524288 | 219 | 16s | No |
01101 |
01101 |
1:262144 | 218 | 8s | No |
01100 |
01100 |
1:131072 | 217 | 4s | No |
01011 |
01011 |
1:65536 | 216 | 2s | No |
01010 |
01010 |
1:32768 | 215 | 1s | No |
01001 |
01001 |
1:16384 | 214 | 512 ms | No |
01000 |
01000 |
1:8192 | 213 | 256 ms | No |
00111 |
00111 |
1:4096 | 212 | 128 ms | No |
00110 |
00110 |
1:2048 | 211 | 64 ms | No |
00101 |
00101 |
1:1024 | 210 | 32 ms | No |
00100 |
00100 |
1:512 | 29 | 16 ms | No |
00011 |
00011 |
1:256 | 28 | 8 ms | No |
00010 |
00010 |
1:128 | 27 | 4 ms | No |
00001 |
00001 |
1:64 | 26 | 2 ms | No |
00000 |
00000 |
1:32 | 25 | 1 ms | No |