6.4 CONFIG4


Bit	7	6	5	4	3	2	1	0
	XINST	DEBUG	LVP	STVREN	PPS1WAY		BORV[1:0]
Access	R/W	R/W	R/W	R/W	R/W		R/W	R/W
Reset	1	1	1	1	1		1	1

Bit 7 – XINST Extended Instruction Set Enable

Value	Description
1	Extended Instruction Set and Indexed Addressing mode disabled (Legacy mode)
0	Extended Instruction Set and Indexed Addressing mode enabled

Bit 6 – DEBUG Debugger Enable

Value	Description
1	Background debugger disabled
0	Background debugger enabled

Bit 5 – LVP Low-Voltage Programming Enable

The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose of this rule is to prevent the user from dropping out of LVP mode while programming from LVP mode or accidentally eliminating LVP mode from the Configuration state.

Value	Description
1	Low-Voltage Programming enabled. MCLR/V_PP pin function is MCLR. The MCLRE Configuration bit is ignored.
0	High Voltage on MCLR/V_PP must be used for programming

Bit 4 – STVREN Stack Overflow/Underflow Reset Enable

Value	Description
1	Stack Overflow or Underflow will cause a Reset
0	Stack Overflow or Underflow will not cause a Reset

Bit 3 – PPS1WAY PPSLOCKED One-Way Set Enable

Value	Description
1	The PPSLOCK bit can be cleared and set only once after an unlocking sequence is executed; once PPSLOCK is set, all future changes to PPS registers are prevented
0	The PPSLOCK bit can be set and cleared as needed (unlocking sequence is required)

Bits 1:0 – BORV[1:0] V_DD Domain Brown-out Reset Voltage Selection

Value	Description
11	Brown-out Reset Voltage (V_BOR) set to 1.90V
10	Brown-out Reset Voltage (V_BOR) set to 2.45V
01	Brown-out Reset Voltage (V_BOR) set to 2.7V
00	Brown-out Reset Voltage (V_BOR) set to 2.85V

Name:	CONFIG4
Offset:	30 0003h