1 Silicon Issue Summary

Legend
-
Erratum is not applicable.
X
Erratum is applicable.
PeripheralShort DescriptionValid for Silicon Revision
Rev. ARev. C
DeviceWriting the OSCLOCK Fuse in FUSE.OSCCFG to '1' Prevents Automatic Loading of Calibration ValuesXX
ADCADC Functionality Cannot be Ensured with CLKADC Above 1.5 MHz and a Setting of 25% Duty CycleXX
ADC Performance Degrades with CLKADC Above 1.5 MHz and VDD < 2.7VXX
One Extra Measurement Performed After Disabling ADC Free-Running ModeXX
CCLConnecting LUTs in Linked Mode Requires OUTEN Set to ‘1’X-
D-latch is Not FunctionalX-
The CCL Must be Disabled to Change the Configuration of a Single LUTXX
NVMCTRLWrong Reset Value of NVMCTRL.CTRLA RegisterXX
RTCDisabling the RTC Stops the PITX-
TCARestart Will Reset Counter Direction in NORMAL and FRQ ModeXX
TCBMinimum Event Duration Must Exceed the Selected Clock PeriodXX
The TCA Restart Command Does Not Force a Restart of TCBXX
CCMP and CNT Registers Act as 16-Bit Registers in 8-Bit PWM ModeXX
TCDAsynchronous Input Events Not Working When TCD Counter Prescaler is UsedXX
Halting TCD and Waiting for SW Restart Does Not Work if Compare Value A is ‘0’ or Dual Slope Mode is UsedXX
USARTTXD Pin Override Not Released When Disabling the TransmitterXX
Frame Error on a Previous Message May Cause False Start Bit DetectionX-
Open-Drain Mode Does Not Work When TXD is Configured as OutputXX
Full Range Duty Cycle Not Supported When Validating LIN Sync FieldX-
Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode-X
Receiver Non-Functional after Detection of Inconsistent Synchronization Field-X

The following silicon revision was never released to production: Rev. B