3 Status of the Synthesis Process

Understanding the synthesis status indicator

A synthesis process converts a logic design into bitstream form which can be loaded into the CLB. This is triggered by clicking the Synthesize button.

The outcome of the synthesis process is indicated by the status indicator and the resource view.

Successful Synthesis

A green indicator will show when the synthesis succeeds and the resource view is updated.

The resource view indicates how much of the CLBs resources have been used, and hovering the mouse over it gives additional information.

Failed Synthesis

A red indicator will show when synthesis has failed.

The nature of the failure can be determined by:

Checking the problems/notifications panels for warnings about unconnected pins
Downloading the ZIP and checking the backend log output. This must also be included when consulting Microchip support channels.

Tip: Selecting the entry in the Problems panel highlights the component or port that is causing the problem.

Resource Usage Debugging

Resource allocation when using the CLB Synthesizer is done by the place and route algorithm in the backend synthesis process. Determining the reason for failure can be complicated, since there are some resources which are locked to individual BLE outputs or a range of BLE outputs. Therefore, a small logic design cannot be synthesized if these resources are in conflict (technically this is a failure to complete place-and-route). In cases where synthesis fails, these actions can be taken to try to alleviate the conflict and reach a solution:

Try to use alternative outputs (eg: change IRQ0 to IRQ1)
Try to remove some logic functionality
Check that there are no unused modules included in the documents
Check that there are no logic functions with pre-determined outputs (eg: a constant zero as an input to an AND gate)

When contacting Microchip support, include the ZIP file which was returned from the failing synthesis process.