5 Interacting with Peripherals and the CPU
How to make connections between the CLB, CPU and other peripheral modules.
5.1 Interacting with Peripherals
Interaction with other peripherals is done by using the input ports from other peripherals and output ports to other peripherals in a logic design. Consult the device datasheet for information on how these signals are used by the corresponding peripheral.
5.1.1 Input Synchronizers
Making use synchronizers on input signals
The CLB peripheral includes 16 input sources, which connects the CLB to external signals, in addition to the 32 CLBSWIN signals for interacting with the CPU. The 16 input sources include modifiers which can be used to condition the incoming signal before it enters the BLE matrix.
Input synchronizer options are selected on the right side properties panel below the input port source selection box.
The available input synchronizer options are shown in the following table:
| Option | Description |
|---|---|
| Synchronized input | The input signal will be synchronized to the CLB clock. This is the defaut, and the safest option when unsure. |
| Direct input | Synchronization is bypassed, and the input signal is connected directly to the BLE input. This must be used with caution as it can cause metastability in sequential logic designs. |
| Positive edge detector | A rising edge on the input signal will generate a pulse synchronized to the CLB clock |
| Negative edge detector | A falling edge on the input signal will generate a pulse synchronized to the CLB clock |
- The CLBSWIN signals cannot pass through the input synchronizers
- The input synchronizer is selected in hardware with three configuration bits, but not all eight possible permutations are made available in the CLB Synthesizer
5.1.2 CLB Outputs to other Peripherals
How to route signals from the CLB to other peripheral modules
The CLB BLE outputs can be connected to various other peripherals. This is a two-stage process:
Step 1: Configure an output from the CLB
In the CLB Synthesizer GUI, configure an output port by selecting the peripheral signal to route to in the port properties panel.
Synthesize the logic design.
Step 2: Configure the peripheral to accept the signal from the CLB
The peripheral to which the CLB is connecting must be configured to accept the CLB input signal. This is Peripheral-dependent, consult the datasheet for more information.
The peripheral input selector usually specified a range of BLEs which can be used as inputs from the CLB. It is not up to the user to specify this - the place and route algorithm must hit one of these BLEs to satisfy the criteria to use the peripheral. The actual BLE which was realized during synthesis receives the synthesis output.
MCC Users
MCC will automatically unpack the output from the synthesis process and notify the user on how to configure the peripherals being connected to. Check the Notifications window after synthesis.
Web/Bare-Metal Users
Users of the web version need to download the ZIP output from the synthesis process and examine (or use directly) the contents of clb1_output_mappings.h file, which provides values for use in the peripheral configuration register.
5.2 Interacting with the CPU
Interaction between the CPU (running code) and the CLB using the CLBSWIN register.
5.2.1 Using CLBSWIN
How to use CLBSWIN from the MCU
The CLB Software Input register (CLBSWIN) enables the MCU to communicate directly with the logic design in the CLB. So for example, this can be used to load a 'value' into the CLB at run time.
To make use of the CLBSWIN register within a logic design, simply use the individual CLBSWINn bits as input ports.
If a logic design needs to trigger an action when a new value is written to CLBSWIN, then the CLBSWIN_SFR_WR_HOLD input signal can be used. This signal is asserted when the CPU writes a new value to CLBSWIN and that value have been latched into the CLB.
- The CLBSWIN register cannot be used via the input synchronizers
- The CLBSWIN_SFR_WR_HOLD signal is asserted only when the lower eight bits of CLBSWIN are written (CLBSWINL), so the byte must be written after writing the upper bytes in CLBSWIN