25.2.4.1.6 Stop Condition Timing
A Stop condition (see Figure 25-29) is
asserted on the SDA pin at the end of a receive/transmit by setting the Stop Condition
Enable (PEN) bit. At the end of a receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA
line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts
down to ‘0
’. When the Baud Rate Generator times
out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover
count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is
high, the P bit is set. One TBRG later, the PEN bit is cleared and the SSPxIF
bit is set.