25.2.5.1.3 Bus Collision During a Stop Condition
Bus collision occurs during a Stop condition if:
- After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out (see Figure 25-40).
- After the SCL pin is deasserted, SCL is sampled low before SDA goes high (see Figure 25-41).
The Stop condition begins with SDA asserted low. When SDA is sampled
low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the
Baud Rate Generator is loaded with SSPxADD and counts down to zero. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master
attempting to drive a data ‘0’ (see Figure 25-40). If
the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs.
This is another case of another master attempting to drive a data ‘0’ (see Figure 25-41).
