41 Revision History

Revision A (9/2015): Initial Release.

Revision B (5/2016): Updated Example 11-6; Figures 37-1, 37-2, 37-5; Register 31-5; Sections 1.1.2, 21.4.1, 21.4.2, 22.1.3, 22.1.9, 22.1.10, 37.2; Tables 37-1, 37-2, 37-3, 37-7, 37-8, 37-9, 37-11, 37-13; Removed Register 5-3; Added long name bit/short name bits section 1.4 and updated bit names accordingly.

Revision C (9/2016):  Updated Peripheral Module, Memory and Core features descriptions on cover page; Updated the PIC18(L)F2x/4xK40 Family Types table; Updated Examples 11-1, 11-3, 11-5 and 11-6; Figures 14-1 and 31-2; Registers 4-2, 4-5, 13-18 and 31-6; Sections 1.2, 4.4.1, 4.5, 4.5.4, 17.3, 17.5, 17.7, 18.1, 18.1.1, 18.1.1.1, 18.1.2, 18.1.6, 18.3, 18.4, 18.7, 19.0, 19.8.1, 20.0, 21.3 and 25.3; Tables 4-2, 37-2, 37-3, 37-5, 37-13 and 37-14.

Revision D (4/2017): Updated Cover page; Updated Example 13-1; Figures 6-1 and 11-11; Registers 3-6, 3-13, 19-1 and 26-9; Sections 1.1.2, 4.3, 13.8, 23.5, 26.5.1, 26.10, 31.1.2 and 31.1.6; Tables 4-1, 10-5, 37-11 and 37-15; New Timer2 Chapter; Removed Section 4.4.2 and 31.2.3; Added Section 23.5.1.

Revision E (10/2017) Updated Cover page; Data sheet format and content updated; Added characteristic graphs.

Revision F (4/2018) Fixed errors in the 44-pin TQFP and QFN pin diagrams; Split TMR0 register (18.6.3) into separate 8-bit registers called TMR0H (18.6.3) and TMR0L (18.6.4); Updated Equation 31-1; Correct typos.