32 ADCC - Analog-to-Digital Converter with Computation Module

The Analog-to-Digital Converter with Computation (ADCC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs that are multiplexed into a single Sample-and-Hold circuit. The output of the Sample-and-Hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRES).

Additionally, the following features are provided within the ADC module:

  • 8-bit Acquisition Timer
  • Hardware Capacitive Voltage Divider (CVD) support:
    • 8-bit precharge timer
    • Adjustable Sample-and-Hold capacitor array
    • Guard ring digital output drive
  • Automatic Repeat and Sequencing:
    • Automated double sample conversion for CVD
    • Two sets of Result registers (Result and Previous Result)
    • Auto-conversion trigger
    • Internal retrigger
  • Computation Features:
    • Averaging and low-pass filter functions
    • Reference comparison
    • 2-level threshold comparison
    • Selectable interrupts

Figure 32-1 shows the block diagram of the ADC.

The ADC voltage reference is software selectable to be either internally generated or externally supplied.

The ADC can generate an interrupt upon completion of a conversion and upon threshold comparison. These interrupts can be used to wake up the device from Sleep.

Figure 32-1. ADCC Block Diagram