27.1.6.10 Gated Counter Mode

This mode counts rising edges on the SMT_signal input, gated by the SMT_window input. It increments the SMTxTMR register for each rising edge of the SMT_signal input while the SMT_window input is high. The SMTxTMR register value is written to the SMTxCPW register upon a falling edge of the SMT_window input. Refer to the figures below.

Figure 27-19. Gated Counter Mode, Repeat Acquisition Timing Diagram

Figure 27-20. Gated Counter Mode, Single Acquisition Timing Diagram