27.1.6.2 Gated Timer Mode

Gated Timer mode uses the SMT_signal input, selected with the SSEL bits, to control whether or not the SMTxTMR register will increment. Upon a falling edge of the signal, the SMTxCPW register will update to the current value of the SMTxTMR register. Example waveforms for both repeated and single acquisitions are provided in the figures below.

Figure 27-4. Gated Timer Mode, Repeat Acquisition Timing Diagram

Figure 27-5. Gated Timer Mode, Single Acquisition Timing Diagram