37.5.3 I2CxCON2

I2C Control Register 2
Name: I2CxCON2
Offset: 0x0296

Bit 76543210 
 ACNTGCENFMEABDSDAHT[1:0]BFRET[1:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – ACNT  Auto-Load I2C Count Register Enable

ValueDescription
1 The first transmitted/received byte after the address is automatically loaded into the I2CxCNT register
0 Auto-load of I2CxCNT is disabled

Bit 6 – GCEN  General Call Address Enable (used when MODE = 00x or MODE = 11x)

ValueDescription
1 General Call Address (0x00) causes an address match event
0 General Call Addressing is disabled

Bit 5 – FME Fast Mode Enable

ValueDescription
1 SCL frequency (FSCL) = FI2CxCLK/4
0 SCL frequency (FSCL) = FI2CxCLK/5

Bit 4 – ABD Address Buffer Disable

ValueDescription
1 Address buffers are disabled.

Received address is loaded into I2CxRXB, address to transmit is loaded into I2CxTXB.
0 Address buffers are enabled.

Received address is loaded into I2CxADB0/I2CxADB1, address to transmit is loaded into I2CxADB0/I2CxADB1.

Bits 3:2 – SDAHT[1:0] SDA Hold Time Selection

ValueDescription
11 Reserved
10 Minimum of 30 ns hold time on SDA after the falling SCL edge
01 Minimum of 100 ns hold time on SDA after the falling SCL edge
00 Minimum of 300 ns hold time on SDA after the falling SCL edge

Bits 1:0 – BFRET[1:0] Bus Free Time Selection

ValueDescription
11 64 I2CxCLK pulses
10 32 I2CxCLK pulses
01 16 I2CxCLK pulses
00 8 I2CxCLK pulses