37.5.11 I2CxCNT

I2C Byte Count Register^(1,2)

Note:

It is recommended to write this register only when the module is Idle (MMA = 0 or SMA = 0) or when the module is clock stretching (CSTR = 1 or MDR = 1).
CNTIF is set on the 9th falling SCL edge when I2CxCNT = 0.

Name:	I2CxCNT
Offset:	0x028C


Bit	15	14	13	12	11	10	9	8
	CNT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:0 – CNT[15:0] Byte Count

Name	Description
If receiving data:	Count value decremented on 8th falling SCL edge when a new byte is loaded into I2CxRXB
If transmitting data:	Count value is decremented on the 9th falling SCL edge when a new byte is moved from I2CxTXB

It is recommended to write this register only when the module is Idle (MMAHost Mode Active Status = 0 or SMAClient Mode Active Status = 0) or when the module is clock stretching (CSTR Client Clock Stretching(3) = 1 or MDR Host Data Request (Host pause) = 1). CNTIF Byte Count Interrupt Flag(1) is set on the 9th falling SCL edge when I2CxCNT = 0.