37.5.11 I2CxCNT

I2C Byte Count Register(1,2)

Note:
  1. It is recommended to write this register only when the module is Idle (MMA = 0 or SMA = 0) or when the module is clock stretching (CSTR = 1 or MDR = 1).
  2. CNTIF is set on the 9th falling SCL edge when I2CxCNT = 0.
Name: I2CxCNT
Offset: 0x028C

Bit 15141312111098 
 CNT[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 CNT[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 15:0 – CNT[15:0] Byte Count

NameDescription
If receiving data: Count value decremented on 8th falling SCL edge when a new byte is loaded into I2CxRXB
If transmitting data: Count value is decremented on the 9th falling SCL edge when a new byte is moved from I2CxTXB
It is recommended to write this register only when the module is Idle (MMAHost Mode Active Status = 0 or SMAClient Mode Active Status = 0) or when the module is clock stretching (CSTR Client Clock Stretching(3) = 1 or MDR Host Data Request (Host pause) = 1). CNTIF Byte Count Interrupt Flag(1) is set on the 9th falling SCL edge when I2CxCNT = 0.