37.5.6 I2CxPIR

I2C Interrupt Flag Register
Note:
  1. Enabled interrupt flags are OR’ed to produce the PIRx[I2CxIF] bit.
  2. ACKTIF is not set by a matching 10-bit high address byte with the R/W bit clear. It is only set after the matching low address byte is shifted in.
Name: I2CxPIR
Offset: 0x029A

Bit 76543210 
 CNTIFACKTIF WRIFADRIFPCIFRSCIFSCIF 
Access R/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HS 
Reset 0000000 

Bit 7 – CNTIF  Byte Count Interrupt Flag(1)

ValueDescription
1 Set on the 9th falling SCL edge when I2CxCNT = 0
0 I2CxCNT value is not zero

Bit 6 – ACKTIF  Acknowledge Status Time Interrupt Flag (used only when MODE = 0xx or MODE = 11x)(1,2)

ValueDescription
1 Acknowledge sequence detected, set on the 9th falling SCL edge for any byte when addressed as a client
0 Acknowledge sequence not detected

Bit 4 – WRIF  Data Write Interrupt Flag (used only when MODE = 0xx or MODE = 11x)(1)

ValueDescription
1 Data byte detected, set on the 8th falling SCL edge for a received data byte
0 Data byte not detected

Bit 3 – ADRIF  Address Interrupt Flag (used only when MODE = 0xx or MODE = 11x)(1)

ValueDescription
1 Address detected, set on the 8th falling SCL edge for a matching received address byte
0 Address not detected

Bit 2 – PCIF  Stop Condition Interrupt Flag(1)

ValueDescription
1 Stop condition detected
0 Stop condition not detected

Bit 1 – RSCIF  Restart Condition Interrupt Flag(1)

ValueDescription
1 Restart condition detected
0 Restart condition not detected

Bit 0 – SCIF  Start Condition Interrupt Flag(1)

ValueDescription
1 Start condition detected
0 Start condition not detected
Enabled interrupt flags are OR’ed to produce the PIRx[I2CxIF] bit. ACKTIF is not set by a matching 10-bit high address byte with the R/W bit clear. It is only set after the matching low address byte is shifted in.