28.9.1 TUxyCON0
Note:
- The selected clock will be enabled when this bit is set and a Start condition has occurred.
- When this bit is set and CSYNC =
1
, it takes three timer clocks to synchronize. When this bit is cleared and CSYNC =1
, the selected clock source (especially external clock sources) must supply at least three additional clocks to resolve internal states. During this time, if the timer is already running, any stop/Reset related ERS events that get processed will continue to affect the Run state of the timer. If CSYNC =0
, the ON bit clears immediately and the timer stops immediately. - This bit is not clock synchronized
and only needs to be changed while ON =
0
. - The purpose of this control is to select the active edge when using externally-clocked Counter mode.
- This bit controls the output even
when ON =
0
. - This bit is shadowed when the module is frozen during debugging and restored when the module resumes operation.
- Capture or stop events load the TUxyCR capture register, regardless of this bit’s setting.
- The effect of writing to TUxyCR
with RDSEL =
0
is not defined. - The interrupt flags will be set even if the corresponding interrupt is disabled.
- The PRIF interrupt will not occur if the user writes the PR value to the TUxyTMR counter register directly.
- The CIF interrupt trigger requires a running timer.
- This register is not available when the module is chained and operated as a Secondary module.
Name: | TUxyCON0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ON | CPOL | OM | OPOL | RDSEL | PRIE | ZIE | CIE | ||
Access | R/W/HC | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – ON Timer Enable(1,2)
Reset States: |
|
Value | Description |
---|---|
1 | The module is enabled |
0 | The module is disabled and in the lowest power mode |
Bit 6 – CPOL Timer Clock Polarity Select(3,4)
Reset States: |
|
Value | Description |
---|---|
1 | The counter advances with the clock rising edge |
0 | The counter advances with the clock falling edge |
Bit 5 – OM Timer Output Mode Select
Reset States: |
|
Value | Description |
---|---|
1 | Output is in Level mode |
0 | Output is in Pulse mode |
Bit 4 – OPOL Timer Output Polarity Select(5)
Reset States: |
|
Value | Description |
---|---|
1 | Output is high when the timer is Idle |
0 | Output is low when the timer is Idle |
Bit 3 – RDSEL Timer Readout Mode Select(6,7,8)
Reset States: |
|
Value | Description |
---|---|
1 | TUxyTMR reads/write the value of the raw counter |
0 | TUxyCR reads the value of the capture register |
Bit 2 – PRIE Period Match Interrupt Enable(9,10)
Reset States: |
|
Value | Description |
---|---|
1 | PRIF interrupt will occur when the counter increments from PR-1 to PR |
0 | PRIF interrupt is disabled |
Bit 1 – ZIE Zero Interrupt Enable(9)
Reset States: |
|
Value | Description |
---|---|
1 | ZIF interrupt will occur when the counter becomes zero from a nonzero value |
0 | ZIF interrupt is disabled |
Bit 0 – CIE Capture Interrupt Enable(9,11)
Reset States: |
|
Value | Description |
---|---|
1 | CIF interrupt will occur when a capture event occurs |
0 | CIF interrupt is disabled |