28.9.4 TUxyPS

Prescaler Value Register
Note:
  1. This register needs to only be written when ON = 0.
  2. This register is not available when the module is chained and operated as a Secondary module.
  3. The internal prescaler counter (not the TUxyPS register) is reset by any Stop or Reset event and upon any write to the TUxyPS and TUxyTMR registers. This allows the next timer interval to be full-length.
Name: TUxyPS

Bit 76543210 
 PS[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 7:0 – PS[7:0]  Clock Prescaler Register

Reset States: 
POR/BOR = 00000000
All Other Resets = uuuuuuuu
ValueDescription
0xFF to 0x01 Divider ratio is (PS+1):1
0x00 The input clock is not divided (1:1 clocking)
This register needs to only be written when ON = 0. This register is not available when the module is chained and operated as a Secondary module. The internal prescaler counter (not the TUxyPS register) is reset by any Stop or Reset event and upon any write to the TUxyPS and TUxyTMR registers. This allows the next timer interval to be full-length.