28.9.5 TUxyTMR (16-bit)

Timer Counter Register for 16-bit version of UTMR module. This register can only be addressed when RDSEL = 1.
Note:
  1. Writing to this register will change the raw counter value directly. The user must handle the operation correctly to avoid data corruption. There is no safeguard for atomic access. Reading or writing a running counter is not recommended. This register must only be accessed while clocking is disabled.
  2. The individual bytes in this multibyte register can be accessed with the following register names:
    • TUxyTMRH: Accesses the high byte TUxyTMR[15:8]
    • TUxyTMRL: Accesses the low byte TUxyTMR[7:0]
Name: TU16yTMR
Offset: 0x38B,0x397

Bit 15141312111098 
 TMR[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 TMR[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 15:0 – TMR[15:0] Timer value

Reset States: 
POR/BOR = 0000000000000000
All Other Resets = uuuuuuuuuuuuuuuu
NameDescription
RDSEL = 1 The raw counter register is read or written; must only be accessed while clocking is disabled, i.e., when ON = 0
RDSEL = 0 Reserved. Do not use.
Writing to this register will change the raw counter value directly. The user must handle the operation correctly to avoid data corruption. There is no safeguard for atomic access. Reading or writing a running counter is not recommended. This register must only be accessed while clocking is disabled. The individual bytes in this multibyte register can be accessed with the following register names: TUxyTMRH: Accesses the high byte TUxyTMR[15:8] TUxyTMRL: Accesses the low byte TUxyTMR[7:0]