27.2.1 SMTxCON0

SMT Control Register 0
Name: SMTxCON0
Offset: 0x030C

Bit 76543210 
 EN STPWPOLSPOLCPOLPS[1:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 7 – EN SMT Enable

ValueDescription
1 SMT is enabled
0 SMT is disabled; internal states are reset, clock requests are disabled

Bit 5 – STP SMT Counter Halt Enable

ValueNameDescription
1 When SMTxTMR = SMTxPR Counter remains at SMTxPR; period match interrupt occurs when clocked
0 When SMTxTMR = SMTxPR Counter resets to 0x000000; period match interrupt occurs when clocked

Bit 4 – WPOL SMT_window Input Polarity Control

ValueDescription
1 SMT_window input is active-low/falling edge enabled
0 SMT_window input is active-high/rising edge enabled

Bit 3 – SPOL SMT_signal Input Polarity Control

ValueDescription
1 SMT_signal input is active-low/falling edge enabled
0 SMT_signal input is active-high/rising edge enabled

Bit 2 – CPOL SMT Clock Input Polarity Control

ValueDescription
1 SMTxTMR increments on the falling edge of the selected clock signal
0 SMTxTMR increments on the rising edge of the selected clock signal

Bits 1:0 – PS[1:0] SMT Prescale Select

ValueDescription
11 Prescaler = 1:8
10 Prescaler = 1:4
01 Prescaler = 1:2
00 Prescaler = 1:1