37.3.14.2 Condition-Specific Interrupts
In addition to the high-level interrupts, module hardware provides several condition-specific interrupts.
The I2C Peripheral Interrupt (I2CxPIR) Register contains the following interrupt flag bits:
- CNTIF: Byte Count Interrupt Flag
- ACKTIF: Acknowledge Status Time Interrupt Flag
- WRIF: Data Write Interrupt Flag
- ADRIF: Address Interrupt Flag
- PCIF: Stop Condition Interrupt Flag
- RSCIF: Restart Condition Interrupt Flag
- SCIF: Start Condition Interrupt Flag
When any of the flag bits in I2CxPIR becomes set and the associated interrupt enable bits in I2CxPIE are set, the generic I2CxIF is also set. If the generic I2CxIE bit is set, an interrupt event is generated whenever one of the I2CxPIR flag bits becomes set. If the I2CxIE bit is clear, the I2CxPIR flag bit will still be set by hardware; however, no interrupt event will be triggered.
1) when the I2CxCNT
register value reaches zero, indicating that all data bytes in the I2C packet
have been transmitted or received. CNTIF is set after the 9th falling SCL edge when
I2CxCNT reaches zero (I2CxCNT = 0).1) by the 9th falling edge of SCL
for any byte when the device is addressed as a client in any Client or Multi-Host mode.
If the Acknowledge Interrupt and Hold Enable (ACKTIE) bit is set and ACKTIF becomes set:- If an ACK is
detected, clock stretching is also enabled (CSTR =
1) - If a NACK is detected, no clock
stretching occurs (CSTR =
0)
1) after the 8th falling edge of SCL
when the module receives a data byte in Client or Multi-Host modes. Once the data byte
is received, WRIF is set, as is the Receive Buffer Full Status (RXBF) and the I2CxRXIF bits, and if the Data Write Interrupt and Hold Enable
(WRIE) bit is set, the generic I2CxIF bit is also set. WRIF is a
read/write bit and must be cleared in software, while the RXBF, I2CxRXIF and I2CxIF bits are read-only and are cleared by reading
I2CxRXB
or by setting the Clear Buffer bit (CLRBF = 1).In addition to the I2CxPIR register, the I2C Error (I2CxERR) register contains three interrupt flag bits that are used to detect bus errors. These read/write bits are set by module hardware, but must be cleared by user software. The I2CxERR register also includes the interrupt enable bits for these three Error conditions and, when set, will cause an interrupt event whenever the associated interrupt flag bit becomes set.
I2CxERR contains the following interrupt flag bits:
- BTOIF: Bus Time-Out Interrupt Flag
- BCLIF: Bus Collision Interrupt Flag
- NACKIF: NACK Detect Interrupt Flag
1) and a bus time-out event occurs
(regardless of the state of the Client Mode Active (SMA)
bit), the module is immediately reset, the SMA and Client Clock Stretching (CSTR) bits are cleared, and the BTOIF bit is set. If the Bus Time-Out
Interrupt Enable (BTOIE)
bit is set, the generic I2C Error Interrupt Flag (I2CxEIF) bit is set.If the module is configured in Client mode with TOREC clear (TOREC = 0) and a bus time-out event occurs
(regardless of the state of the Client Mode Active (SMA)
bit), the BTOIF bit is set, but user software must reset the module. If the Bus Time-Out
Interrupt Enable (BTOIE)
bit is set, the generic I2C Error Interrupt Flag (I2CxEIF) bit is set.
1) and the bus time-out event occurs
while the Host is active (Host Mode Active (MMA) =
1), the Host Data Ready (MDR)
bit is cleared, the module will immediately attempt to transmit a Stop condition, and
the BTOIF bit is set. Stop condition generation may be delayed if a client device is
stretching the clock but will resume once the clock is released or if the client holding
the bus also has a time-out event occur. The MMA bit is only cleared after the Stop
condition has been generated. If the Bus Time-Out Interrupt Enable (BTOIE)
bit is set, the generic I2C Error Interrupt Flag (I2CxEIF) bit is set.0) and the bus time-out event occurs
while the Host is active (Host Mode Active (MMA) =
1), the MDR bit
is cleared and the BTOIF bit is set, but user software must initiate the Stop condition
by setting the P bit.
If the Bus Time-Out Interrupt Enable (BTOIE)
bit is set, the generic I2C Error Interrupt Flag (I2CxEIF) bit is set.1 || MMA =
1) and a NACK response is detected on the bus. A NACK response
occurs during the 9th SCL pulse in which the SDA line is released to a logic high. In
Host mode, a NACK can be issued when the host has finished receiving data from a client
or when the host receives incorrect data. In Client mode, a NACK is issued when the
client does not receive a matching address or when it receives incorrect data. A NACK
can also be automatically issued when any of the following bits becomes set, which will
also set NACKIF and I2CxEIF:- TXWE: Transmit Write Error Status
- RXRE: Receive Read Error Status
- TXU: Transmit Underflow Status
- RXO: Receive Overflow Status