26.10.3 TxCON

Note:
  1. In certain modes, the ON bit will be auto-cleared by hardware. See Table 26-1.
Name: TxCON
Offset: 0x324,0x330,0x33C

Timerx Control Register

Bit 76543210 
 ONCKPS[2:0]OUTPS[3:0] 
Access R/W/HCR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – ON  Timer On(1)

ValueDescription
1

Timer is on
0

Timer is off: All counters and state machines are reset

Bits 6:4 – CKPS[2:0] Timer Clock Prescale Select

ValueDescription
111

1:128 Prescaler
110

1:64 Prescaler
101

1:32 Prescaler
100

1:16 Prescaler
011

1:8 Prescaler
010

1:4 Prescaler
001

1:2 Prescaler
000

1:1 Prescaler

Bits 3:0 – OUTPS[3:0] Timer Output Postscaler Select

ValueDescription
1111

1:16 Postscaler
1110

1:15 Postscaler
1101

1:14 Postscaler
1100

1:13 Postscaler
1011

1:12 Postscaler
1010

1:11 Postscaler
1001

1:10 Postscaler
1000

1:9 Postscaler
0111

1:8 Postscaler
0110

1:7 Postscaler
0101

1:6 Postscaler
0100

1:5 Postscaler
0011

1:4 Postscaler
0010

1:3 Postscaler
0001

1:2 Postscaler
0000

1:1 Postscaler
In certain modes, the ON bit will be auto-cleared by hardware. See Table   1.