10.3.1 Standard Communication

The main interface to the target processor is via standard communication. It contains the connections to the VDD reset, clock and data connections that are required for programming and connecting with the target devices.

The clock and data connections are interfaces with the following characteristics:

  • Clock and data signals are in high-impedance mode (even when no power is applied to the MPLAB Snap In-Circuit Debugger system).
Table 10-3. Electrical Logic Table
Logic InputsVIH = VDD x 0.7V (min.)
VIL = VDD x 0.3V (max.)
Logic Outputs VDD = 5V VDD = 3V VDD = 2.3V VDD = 1.4V
VOH = 3.8V min. VOH = 2.4V min.VOH = 1.9V min.VOH = 1.0V min.
VOL = 0.55V max.VOL = 0.55V max.VOL = 0.3V max.VOL = 0.1V max.
Figure 10-2. Debugger Connector Pinout