Silicon Errata Issues

The PIC32CX-BZ3 Power Management Unit (PMU) supports only the MLDO mode only. The PIC32CX-BZ36 Power Management Unit (PMU) supports both MLDO and Buck mode.

The system is not entering the Sleep mode when the Flash power down (NVMCON2.SLEEP = 0) bit is disabled and system is working at equal to or less than the FRC frequency.

In the Deep Sleep and Extreme Deep Sleep modes, GPIO must not be set to the output state of pin HIGH.

Configuring the GPIO state to pin High during the Deep Sleep and Extreme Deep Sleep modes will cause leakage current and potential reliability issues on the silicon.

This issue is only applicable when the CPU is in the Deep Sleep/Extreme Deep Sleep mode and when GPIO is configured as the output state pin HIGH.

Issue occurs when CNEN0x = 110 or 101. Device would not wake up on pin state change

CNEN0x = 110, interrupt on change for a negative edge transition is enabled for PORTx[n]

CNEN0x = 101, interrupt on change for a positive edge transition is enabled for PORTx[n]

The POR event is not getting triggered even when the voltage is going below 1.45V.

Analog Comparator output (AC_CMPx) will not be disabled by setting either COMPCTRLx.ENABLE = 0 or PMD1.ACMD = 1.

AC_CMP0 uses a fixed VDD/2 reference, but the observed reference voltage is not equal to VDD/2.

Incorrect VDD scaler reference voltage is observed when AC_CMP0 and AC_CMP1 are enabled concurrently with VDD scaler as reference for both the comparators. Both the comparators will see the same VDD scaler reference.

The scan list conversions defined in the ADCCSS1 register will restart without finishing the current scan list and does not generate an EOSRDY bit (ADCCON2[29]) end of scan interrupt status if a new trigger event from the STRGSRC[4:0] bits (ADCCON1[20:16]) trigger source occurs before the scan list completion on the shared ADC core.

A comparison in single shot mode will not be completed when entering in Standby sleep mode with RUNSTDBY=0.

When the ADC Control clock is asynchronous with the System clock, the conversion result may have glitches if the CPU reads ADCBUFx while a new conversion result is being updated.

The ADC internal input channel, AN11, is connected with VDD33/2, but the observed input voltage is not equal to VDD/2.

When the LUT is disabled (LUTCTRL0.ENABLE=0 or LUTCTRL2.ENABLE=0) to clear the flip-flop/latch output, then enabled again, the sequential logic is kept under Reset.

Writing the Software Reset bit in the control register (CTRL.SWRST) will trigger a PAC protection error.

Invalid CVD event can get created while FIFO counter is incrementing.

Writeback descriptors could be corrupted on an active channel with ongoing transfers when another channel is being disabled or suspended.

When at least one channel using linked descriptors is already active, a channel Fetch Error (FERR) may occur upon enabling a channel with no linked descriptor or the second descriptor (index 1) of the channel being enabled may be fetched by one of the already active channels using linked descriptors. These errors may happen when a channel is being enabled during the link request of another channel and if the channel number of the channel being enabled is lower than the channel already active.

When the asynchronous edge detection is enabled (without debouncer), and the system is in the Standby Sleep mode, only the first edge will generate an event. The edges following the first edge of the waveform do not generate events until the system wakes up.

If the NMI is configured in synchronous edge detection mode (NMICTR.NMISENSE = 1, 2 or 3; NMICTRL.NMIASYNCH = 0), spurious NMI interrupts may occur after a software reset (CTRLA.SWRST = 1).

BUSYCH flag never resets upon software events in synchronous/resynchronized path modes with event detection on falling edges.

If a software event occurs when the EVSYS is set in synchronous/resynchronized path modes (CHANNELn.PATH = 0x0/0x1) with event detection set on falling edges (CHANNELn.EDGSEL = 0x2), the CHSTATUS.BUSYCHn flag will be set but will never come back to 0. It is, then, impossible to know if the event user for this channel is ready or not to accept new events.

The overrun interrupt flag may be incorrectly set upon software events in synchronous/resynchronized path modes with event detection on both rising and falling edges.

If a software event occurs when the EVSYS is set in synchronous/resynchronized path modes (CHANNELn.PATH = 0x0/0x1) with event detection set on both rising and falling edges (CHANNELn.EDGSEL = 0x3), spurious overrun interrupts may occur (INTFLAG.OVRn).

In the Synchronous mode, spurious overrun interrupts can happen when the generic clock for a channel is always CHANNEL.ONDEMAND = 0.

After the Erase Retry operation (using NVMCON2.VREAD1 = 1), all the operations work as expected until a SYS Reset is asserted. When the SYS Reset is asserted post-Erase Retry, the Reset is stuck and not getting released.

Flash read/write by DMA not working in Standby Sleep mode if Flash power down is enabled.

The NMI wakes while the CRU is entering Sleep mode and may trigger Flash DPD on early wake-up.

Issue occurs when a signal changes on a GPIO pad and at the same time ICD freezes the GPIO peripheral. In this case reading the port register will result in unstable values for the pads that changed.

FREQM reads on the Control B register (FREQM.CTRLB) to generate a PAC protection error.

If PB2_CLK is not equal to System Clock (sys_clk), the QSPI Status register bits are not updated.

If PB2_CLK is not equal to System Clock (sys_clk), the ERRADDR register read will not return the failing address (caused by Single Bit Error/Dual Bit Error). Instead, it may return ‘0’.

When SRAM is configured for memory retention, 6 bytes of memory cannot be retained.

Majority debouncing, as part of RTCC tamper detection, does not work when enabled by setting the Debouncer Majority Enable bit, CTRLB.DEBMAJ.

When COUNTSYNC is enabled, the first COUNT value is not correctly synchronized, and, thus, its value is incorrect.

Majority debouncing, as part of RTCC tamper detection, does not work when enabled by setting the Debouncer Majority Enable bit, CTRLB.DEBMAJ.

When the RTCC is configured in ACTL mode with an external tamper pin (ALSI=0) and the RTCC CTRLA.ENABLE bit is not set, a tamper can be detected and a timestamp captured. The TAMID register and INTFLAG.TAMPER bit may be (not always) set.

If an external Reset occurs during a tamper detection, the TIMESTAMP register will not be updated when the next tamper detection is triggered.

When CTRLA.PRESCALER is set to OFF and either CTRLB.RTCCOUT is set or one of the TAMCTRL.DEBNCn bits is set, the RTCC prescaler behaves like CTRLA.PRESCALER = DIV1. The Periodic events and Periodic interrupts will be generated.

General Purpose Registers n (GPn) are reset on tamper detection even if GPTRST = 0.

When DMA is enabled (CTRLB.DMAEN = 1), the INTFLAG.TAMPER bit is not reset by reading the TIMESTAMP register.

In the USART operating mode with Collision Detection enabled (CTRLB.COLDEN = 1), the SERCOM will not abort the current transfer as expected if a collision is detected and if the SERCOM APB (PBx_CLK) Clock is lower than the SERCOM Generic Clock.

In the USART operating mode, if DBGCTRL.DBGSTOP = 1, data transmission is not halted after entering the Debug mode.

When the USART is used in the 32-bit mode with hardware handshaking (CTS/RTS), the TXC flag may be set before transmission has completed. TXC may incorrectly be set regardless of whether Data Length Enable (LENGTH.LENEN) is set to ‘0’ or ‘1’.

The SERCOM USART does not wake from the Standby Sleep mode for ERROR interrupts FERR and PERR.

When the SERCOM USART is configured as CTRLA.RUNSTDBY = 0 and the Receiver is disabled (CTRLB.RXEN = 0), the clock request to the SERCOM generic clock generator feeding the SERCOM will stay asserted during the Standby Sleep mode, leading to unexpected overconsumption.

In the I²C mode, the LENERR, SEXTOUT, LOWTOUT, COLL and BUSERR bits are not cleared when INTFLAG.AMATCH is cleared.

In the I²C Client Transmitter mode, at the reception of a NACK, if there is still data to be sent in the DMA buffer, the DMA will push data to the DATA register. Because a NACK was received, the transfer on the I ²C bus will not occur, causing the loss of this data.

When SERCOM is configured as an I²C client in the 32-bit Data mode (DATA32B = 1) and the I²C host reads from the I²C client (client transmitter) and outputs its NACK (indicating no more data is needed), the I²C client still receives a DRDY interrupt.

If the CPU does not write a new data to the I²C client DATA register, the I²C client will pull the SDA line, which will result in stalling the bus permanently.

When the Quick command is enabled (CTRLB.QCEN = 1), software can issue a repeated Start by writing either CTRLB.CMD or ADDR.ADDR bit fields. If, in these conditions, the SCL Stretch mode is CTRLA.SCLSM = 1, a bus error will be generated.

SCL/SDA minimum transition time is not met in Fast-mode plus (1 MHz).

When an unexpected STOP occurs on the I²C bus, the STATUS.BUSERR and INTFLAG.ERROR bits are set but may not wake the system from the Standby Sleep mode. An unexpected START will not produce this issue.

The RXNACK status bit is invalid during the first I2CS_DRDY interruption handler.

The RXNACK status bit is invalid during the first I2CS_DRDY interruption handler.

In the SPI Client mode with Client Data Preload Enabled (CTRLB.PLOADEN = 1), the client transmitter may discard some data if the host cannot keep the Client Select pin low until the end of transmission.

When the 32-bit extension mode is enabled and Data to be sent is not in multiples of 4 bytes (which means length counter needs to be enabled). In this case, additional byte(s) will be sent over the line.

Preloading a new SPI data (CTRLB.PLOADEN = 1) before going into the Standby Sleep mode may lead to extra power consumption.

When Hardware Client Select Control is enabled (CTRLB.MSSEN = 1), the Client Select (SS) pin goes high after each byte transfer even if new data is ready to be sent.

Two stop bits mode (CTRLB.SBMODE=0x1) is not supported in SERCOM USART LIN Host Mode (CTRLA.FORM=0x2) in the case where break, sync and identifier fields are automatically transmitted when DATA is written with the identifier (CTRLB.LINCMD=0x2). Only one stop bit mode is supported.

When the TCC is used in the Down-counting mode, transfer of the PERBUF register value to the PER register is delayed by one counter cycle, and, therefore, the LUPD feature must not be used with the PER register.

If a Re-trigger event (EVCTRL.EVACTn = 0x1, RETRIGGER) occurs at the Channel Compare Match [n] time, the next Waveform Output [n] is corrupted.

TCC input events does not support Synchronous or Resynchronized path.

Using the TCC in the Dithering mode with external re-trigger events can lead to an unexpected stretch of right-aligned pulses or shrink of left-aligned pulses.

The Timer/Counter Counting-down mode (CTRLBCLR.DIR = CTRLBSET.DIR = 1) is not supported in RAMP2 operations (RAMP2, RAMP2A, RAMP2C, RAMP2CS).

In 2RAMP mode with Hi-resolution, multiple restarts can be observed when a fault occurs.

When clearing the STATUS.PERBUFV/STATUS.CCBUFx flag, the SYNCBUSY flag is released before the PERBUF/CCBUFx register is restored to its appropriate value.

If a Re-trigger event (EVCTRL.EVACTn = 0x1, RETRIGGER) occurs at the Channel Compare Match [n] time, the next Waveform Output [n] is corrupted.

When the interval between clearing the watchdog timer (in other words, clearing the Run mode watchdog counter) and the sleep instruction is less than 1 WDT clock cycle, the Run mode watchdog counter is not cleared. When using LPRC as a clock source, the interval is 1 LPRC clock. Because the watchdog timer is in the LPRC domain, which is much slower than the CPU clock, the sleep instruction is executed even before the Run mode watchdog counter is cleared. Hence, the Run mode watchdog counter remains frozen to its last count instead of clearing to ‘0’.

While in the Standby Sleep mode, the Sleep mode watchdog counter increments. At the end of the WDTPS, it generates an NMI, which causes the CPU to wake up.

After wake-up, the user will expect that because WDT is cleared just before going to sleep, they have an entire WDT period available to them before they have to clear WDT again, but, because the Run mode counter was not cleared before going into sleep, the WDT Reset occurs earlier than expected.